When someone uses the words “verification” and “FPGA” in the same sentence, I’m always suspicious. In the ASIC design world, where risk avoidance is everything, “verification” is a sacred term. “Verification” is the long pole in the tent, the most time-consuming phase of the design cycle. “Verification” is what you do to protect your job so you’re not blamed with an expensive and time-consuming re-spin of an ASIC design. “Verification” is what EDA companies have learned to trust as their bread-and-butter. Capitalizing on the risk inherent in the ASIC design flow, they produce premium-priced solutions that seek to siphon off the inevitable human failures that find their way into complex engineering projects.

It stands to reason, then, that when FPGA designs began to reach the same complexity as ASIC designs, EDA companies and ASIC designers would have a Pavlovian response, driving them immediately to the question of “verification”. Without so much as a pause to ponder, they mimic the mantras of the ASIC world: “Well, if your FPGA designs are reaching five million gates, you’re going to need some sophisticated verification tools.” [more]

Catapult C
Mentor Announces Architectural Synthesis

Electronic design automation has its own secret little cold fusion. An innovation that everyone quietly hopes is possible but publicly disavows. A development that would make life beautiful, dogs and cats live happily together, and money grow on trees. This missing link is “behavioral synthesis,” the direct compilation of untimed algorithmic descriptions into practical hardware architectures. Once this is possible, digital hardware designers, the micro-architectural mavens that create much of the magic in today’s ASIC and FPGA designs, will no longer be necessary. All of their relevant expertise, tricks and techniques will be encapsulated in a powerful software application that will dash out optimized datapaths on Monday morning without a sip of caffeine, and crank out perfectly designed hardware all week without asking for a raise or a better 401-K package. Any competent software engineer will be able to fish a function out of their latest C++ application and recompile it for hardware implementation with a 1000X performance boost.

While this prospect may sound both thrilling and terrifying to experts in VHDL- and Verilog-based hardware design, there has never been reason for serious concern. The technical challenges posed by this problem have created in EDA something akin to Fermat’s Last Theorem, with a similar number of false announcements of success. There have been, in fact, enough premature, false, and exaggerated claims that the term “behavioral synthesis” has become so maligned that marketers won’t touch it. New products that use some behavioral synthesis technology are simply described as “automatically creating RTL” or “from algorithm to architecture”. [more]

Leveraging On-Chip Debug for VME
by Olivier Potin, Project leader, Temento Systems
and Christian Riva, HW Engineer, Galileo Avionica

Galileo Avionica needed an easy-to-use VME BUS monitor that could be used by both hardware and software engineers working on VME-based projects. Using a plug-in VME board with an Altera FPGA, embedded DiaLite virtual instrumentation from Temento Systems, and a TCL/TK-based custom human interface, an innovative solution was crafted that allows simple, multi-use analysis of the VME bus by engineers from different disciplines with widely varied levels of experience and expertise.

This article describes how DiaLite Instrumentation (DLI) was used to build a custom tool by taking advantage of the capability to drive DiaLite via TCL scripts. This capability allowed Gallileo Avionica to use the DiaLite server as the engine for their bus monitor with specific human interfaces developed with TCL/TK. This interface provides interactivity adapted to the language and skill level of a specific user. We will show how to build an embedded VME BUS Monitor whose interface can be for either software engineers or hardware engineers. The monitor will then allow the end-user to describe the triggering and the display of the bus activity according to his own concept of the VME BUS behavior without having to understand concepts such as VHDL code, which may not be in his area of expertise. [more]